Integrated Equalizer and Line Coding
Fraunhofer Institute for Integrated Circuits
Integrated Equalizer and Line Coding
Due to ever increasing data rates – mostly because of video- and multimedia applications – it becomes more and more challenging to transmit these high data rates with conventional data cables. Transmission lines based on copper-based twisted pair cables or on optical multimode- or polymer fibers are all limited both in bandwidth and in signal-to-noise-behaviour. Thus, an adapted line coding scheme with preemphasis in the transmitter and equalization in the receiver has to be applied in order to transmit high data rates with low power and low cost. Therefore, we investigated and implemented several equalizer concepts for transmission of 1.25 Gbit/s and 3.3 Gbit/s in CMOS technology:
- Front-end amplifiers with automatic gain control
- Linear, controlled high pass filters for direct compensation of the transmission channel
- FIR-filter for preemphasis in the transmitter and as feed-forward-equalizer (FFE) in the receiver
- Decision-feedback-equalizer (DFE) in the receiver
- Use of delay locked loops (DLL)
- Control algorithms for blind adaptive control of equalizer coefficients
- Architecture of an equalizer with variable gain stage, linear high-pass-filter and DFE
Mostly, the number of taps for FFE and DFE used was 3 to 6 with a delay varying from one third to the whole clock period, depending on the transmission system. The equalizer parameters are being adapted automatically to the channel by using a blind algorithm (constant modulus algorithm CMA) without the need for calibration with a training sequence. The algorithm can be implemented in an external microprocessor or directly on the chip. An additional stage for clock-and-data-recovery (CDR) ensures a low jitter, high transmission quality. The power consumption of the equalizers e.g. for an implementation in 65 nm-CMOS technology is in the order of 30 mW.
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