Analog/Digital Converter
Fraunhofer Institute for Integrated Circuits
Analog/Digital Converter
Analog digital converters (ADCs) are key components in modern measuring and controlling systems. We continuously develop new ADC macros for application in integrated mixed signal systems.
Typically implementation is done in standard CMOS. ADC macros are combined with precise analog pre-processing and complex digital functions creating a single-chip solution. We use different architectures to achieve the required resolution and efficiency. Our spectrum covers resolutions from 8 to 18 bits and 100 Hz to 100 MHz Nyquist rate.
| Architecture | Resolution | Conversion Rate | Technology |
| Flash | 6 bit | 120 MS/s | 0.35 µm CMOS |
| Pipeline | 12 bit | 40 MS/s | 0.35 µm CMOS |
| SAR | 16 bit | 200 kS/s | 0.6 µm CMOS |
| Delta-Sigma | 16 bit | 60 kS/s | 0.35 µm CMOS |
| Delta-Sigma | 14 bit | 62 kS/s | 0.18 µm CMOS |
Project Examples
- Delta-Sigma Converter
- SAR Converter
- Pipeline Converter
Delta-Sigma Converter
Two second-order modulators with one bit quantification are cascaded in this delta/sigma converter. It features a dynamic range of 102 dB and a SNDR of 93 dB with a resolution of 15 bit.
Further characteristics are listed in the chart below:
| Technology | CMOS 0.35µm DPTM |
| Power Requirement | 6.5 mW |
| Cycle | 4 MHz |
| Nyquist Frequency | 30 kHz |
| Supply Voltage | 3.3 V |
| Oversampling | 64 times |
| Active Chip Area | 1.12 mm² |
Sucessive Approximation Converter
This successive approximation converter uses redistribution of charge to convert the analog input signal. The signal is charged to a capacity, the following conversion is achieved via reallocation of charge to other capacities. This converter is optimized for low power consumption.
Further characteristics are listed in the chart below:
| Technology | CMOS 0.35 µm DPTM |
| Power Requirement | 130 mW |
| Frequency | 40 MHz |
| Supply Voltage | 3.3 V |
| Active Chip Area | 2.4 mm² |
Pipeline Converter
Pipeline converters offer high data rates at high resolution. The converter shown here has 10 levels of 1.5 bit per level (three comparator levels) and digital correction. It is optimized for low power consumption.
Further characteristics are listed in the chart below:
| Technology | CMOS 0.6 µm DPTM |
| Power Requirement | 6,8 mW |
| Cycle | 3,2 MHz |
| Frequency | 200 kHz |
| Supply Voltage | 5,0 V / 2,7 V |
| Active Chip Area | 2 mm² |
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