Tutorial on Silicon-Photonic IC Design in IHPs SG25H4EPIC using a Cadence/IPKISS Design Flow

Course Objectives

An intensive course on electronic-photonic IC (EPIC) design methodology using the IHP design kit SG25H4EPIC

The aim of this course is to enable designers of high performance integrated circuits:

  • to understand the design methodology for electronic-photonic ICs
  • to gain insight into the design flow implemented for the IHP SG25H4EPIC technology

Course contents

  • Electronic-photonic design kit (overview & installation)
  • Schematic & layout of a simple EPIC design     
  • Technology information and MPW tape-in procedure

The practical examples given are based on 0.25 µm SiGe:C photonic BiCMOS technology, Cadence and IPKISS.
Design steps will be practised on workstations.

Course Details

Day 1 - IHP Mixed-Signal Design Flow

  • Introduction to tutorial and IHP silicon photonic MPW service
  • Introduction to the electronic-photonic design kit
  • EPIC design example from schematic to layout (hands-on)
  • Luceda EDA Solution for photonic design
  • Parametric layout of an optical DBPSK receiver with IPKISS
    – Part 1 (hands-on)

Day 2 - IHP Mixed-Signal Design Flow

  • Parametric layout of an optical DBPSK receiver with IPKISS – Part 2 (hands-on)
  • Design kit documentation and support
  • Best practices for electronic-photonic IC design
  • 25 Gbps TIA design example (on abstract level) in an EPIC design flow (hands-on)
  • Q&A

Course participants should be familiar with circuit design. Familiarity with Cadence design tools would be helpful.

Course Language

English 

Date

July 24 - 25, 2018

8:30 to 16:30 with 15:00 finish on the final day (Local times)

Cost

For EUROPRACTICE members: 250 Euro

For non-members: 500 Euro

Location

Technische Universität Berlin
Chair Mixed Signal Circuit Design
Room no. EN414
Einsteinufer 17
10587 Berlin, Germany

Registration

EUROPRACTICE members please register at www.europractice\training.

Non-members please contact Wolfgang Kissinger, IHP, directly via Email.

Registration Deadline: June 24, 2018

The number of participants is limited.

For more information and details please contact virtual-aisic@iis.fraunhofer.de

Download EPIC design methology with IHT design kit SG25H4, July 24-25, 2018