Virtual ASIC Foundry

The Fraunhofer IIS Virtual ASIC Foundry, including its Design Enablement Team within the Chips Joint Undertaking (JU) initiative, enables the cost-effective development and production of customer-specific microchips – even in small quantities. It supports research institutions, start-ups, and small and medium-sized enterprises, for whom access to modern semiconductor technologies is often hampered by high costs, complex processes, and large minimum quantities.

Efficient, low-risk solutions are created through Multi-Project-Wafer and small-volume runs, secure cloud-based of on-premise design environments, close cooperations with foundries and supply-chain partners, and modular support across the complete chip lifecycle. The Virtual ASIC Foundry thus shortens development cycles and creates new scope for innovation and technology transfer by lowering barriers to semiconductor fabrication.

Our services along the entire ASIC life cycle

We act as the central interface between development, foundry, and supply chain, coordinating all process steps and providing access to a broad portfolio of technologies from leading semiconductor manufacturers such as ams OSRAM, GlobalFoundries, IHP – Leibniz Institute for Innovative Microelectronics, United Monolithic Semiconductors (UMS), and X-Fab.

Partner foundry and technology selection

We have been working closely with six leading semiconductor manufacturers for many years to implement ASIC projects. This gives projects direct, cost-efficient access to modern manufacturing technologies through our partners: ams OSRAM, Fraunhofer IISB, GlobalFoundries, IHP, UMS, and X-FAB.

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Overview

Table of Fraunhofer IIS technology portfolio processes and nodes — © Fraunhofer IIS

ams-OSRAM

The ams-OSRAM state-of-the-art 8-inch fab delivers high-performance process technologies backed by over 30 years of wafer processing experience. Their Process Design Kit (PDK) includes all necessary components for developing complex analog mixed-signal designs. The ams 350 nm and 180 nm technologies – featuring standard CMOS, HV, SiGe, and Opto processes – are fabricated in Austria, providing cost-effective and accessible prototyping and small-volume services for both academia and industry.

For more technology details, please click here.

Fraunhofer IISB

Fraunhofer IISB provides early access to its 2µm SiC CMOS technology, featuring NMOS and PMOS transistors, passive components, and pn-diodes for integrated circuits. These circuits can operate in extreme temperatures exceeding 300 °C (up to approximately 600 °C). Additional process modules are available for high-voltage devices, isolated transistors, and SiC device templates that extend beyond traditional CMOS circuits. This technology is ideal for integrated circuits designed for harsh environments, including high temperatures and radiation levels, while minimizing leakage. Furthermore, it can be customized to develop specialized optical SiC devices and quantum sensor templates.

For more technology details, please click here.

GlobalFoundries

GlobalFoundries is the world’s leading specialty foundry, offering a wide range of platforms and features, including RF CMOS, FDSOI, RFSOI, SiGe, FinFET, and SiPhotonics. Technology nodes span from 180 nm to 12 nm, with the 22 nm and 28 nm nodes fabricated in Dresden, Germany. The 22FDX® technology utilizes 22 nm Fully Depleted Silicon-On-Insulator (FD-SOI), delivering exceptional performance at extremely low power, capable of operating at just 0.4V and achieving ultra-low standby leakage of 1 pA per micron.

For more technology details, please click here.

IHP

IHP provides research partners and industrial clients worldwide with access to advanced SiGe:C BiCMOS technologies. They have developed multiple generations of high-speed SiGe Heterojunction Bipolar Transistors (HBT) integrated into 0.25 μm and 0.13 μm BiCMOS processes. Notably, the 0.13 μm process SG13G2 is the fastest SiGe HBT technology available, achieving peak fT / fmax values of 300 GHz / 500 GHz. These technologies excel in higher GHz applications, such as telecommunications, broadband, radar and more.

Additionally, the G25H5_EPIC technology enables monolithic integration of photonic devices—like detectors and modulators—within Si-based integrated circuits, facilitating ultra-short interconnects between photonics and electronics. This integration significantly enhances the performance of Electronic-Photonic Integrated Circuits (EPIC), making it ideal for Optical Transceivers for 100G, 200G, and 400G applications.

For more technology details, please click here.

ums

United Monolithic Semiconductors (UMS) is the European leader in RF MMIC products and foundry services for specialized markets such as Defense and Space, telecommunications, automotive radar, and industrial sensors. UMS offers a comprehensive range of solutions, including ASICs and catalog products built on the company’s proprietary III-V technologies, along with extensive foundry services that enable customers to develop tailored product solutions.

Their catalog features a full spectrum of products from DC to 100 GHz, utilizing GaAs, GaN, and SiGe technologies. This includes power amplifiers up to 200W, mixed-signal functions, very low noise amplifiers, and complete transceiver systems. Products are available in die form but are typically offered packaged or as multichip modules.

For more technology details, please click here.

X-FAB

X-FAB is a global foundry group providing a comprehensive set of specialty technologies and design IP to enable its customers to develop world-leading semiconductor products that are manufactured at X-FAB's six wafer fabs located in Malaysia, Germany, France, and the United States. With its expertise in analog/mixed-signal technologies, microsystems/MEMS, Photonics, silicon carbide (SiC) and gallium nitride (GaN), X-FAB is the development and manufacturing partner for its customers, primarily serving the automotive, industrial and medical end markets. X-FAB has approximately 4,500 employees and has been listed on Euronext Paris since April 2017 (XFAB).

For more technology details, please click here.

Migration to Series

© Titolino – stock.adobe.com / Edited bei Fraunhofer IIS

For projects with a clear commercialization perspective, scaling takes place in dedicated production processes: Engineering runs or full-mask sets enable production on your own wafers - from low-volume batches to several million dies.

Our team provides continuous support for:

Design and yield optimizations
Supply chain coordination
Assembly and testing

Post-Fab Services

Production is followed by project-specific testing and integration measures through our partner ecosystem:

Wafer-level and package tests (single-site and multi-site, including high-volume)
Cooperation with European and global packaging partners for plastic, ceramic and photonic packages
Additional services such as qualification, backgrinding, bumping or customer-specific processes
Short-term storage of small quantities at the institute, larger volumes via logistics partners

European focus, global reach

While our focus clearly lies on Europe – as shown in the graph – we operate globally with a significant number of users from Asia and the Americas. Most designs are manufactured using advanced nodes such as 22nm and SiGe processes, but the pie chart also demonstrates the diversity of our customer demand.

Diagram and pie chart of Fraunhofer IIS tape outs and supported designs per technology — © Fraunhofer IIS

Partnering with EuroCDP and Europractice

Fraunhofer IIS connects two complementary European offerings. Through its interface with the European Chips Design Platform (EuroCDP), customers benefit from secure cloud-based and on-premises design environments, professional EDA tools, integrated Process Design Kits, scalable computing resources and standardized design flows. Through the established Europractice cooperation, universities, public research institutes and eligible small companies gain cost-efficient access to training, prototypes and small-volume production via Multi-Project Wafer runs. Together, these services support projects from the initial concept and IC design through verification and prototyping to transfer into series production.

Chip design for European start-ups and SMEs through EuroCDP

The European Chips Design Platform (EuroCDP) makes it easier for start-ups, small and medium-sized enterprises and research teams in Europe to access the resources needed to develop customer-specific microchips. Building on the experience of Europractice, it brings together access to professional EDA tools, reusable IP blocks, training and expert support. Design Enablement Teams combine secure cloud-based design infrastructure with technical guidance – from setting up the design environment through design and verification to prototyping and fabrication. The Fraunhofer IIS Virtual ASIC Foundry supports this process with modular services throughout the entire chip lifecycle. This approach aims to lower technical and economic barriers to entry and help turn innovative chip concepts into functional products.

Cost-efficient chip prototyping for academia through Europractice

As part of the European Europractice initiative, which has been supporting innovation and training in microelectronics, nanotechnology and photonics since 1995, cost-efficient access to prototypes and small series can be realized. Europractice is specifically available to universities, public research institutes, and small spin‑out companies, enabling these organizations to transition research results into silicon under economically viable conditions. By bundling several designs on one wafer through the multi-project wafer (MPW) approach, Europractice significantly reduces fabrication costs.

Fraunhofer IIS supports you with:

Design, layout and verification
Tape-out coordination
Production of initial samples, typically 25/50/100 units
Small series at fixed, predictable prices
IC design training courses

Proof of concept, pilot projects and early market tests can thus be realized economically.

Further information

IC Design

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IP Cores and Macros

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APECS is co-funded by the Chips Joint Undertaking and national funding authorities from Belgium, Germany, Finland, France, Greece, Austria, Portugal, and Spain under the “Chips for Europe” initiative. This project is supported by the European Union’s European Regional Development Fund (ERDF).

APECS at Fraunhofer IIS