IC Design – IP Cores und Macros

Bei der Entwicklung von ASIC- und SoC-Lösungen reduzieren IPs und Makros die Entwicklungszeit, das Designrisiko und die Kosten. Als unabhängiges Designhaus können wir unseren Kunden Lösungen anbieten, die speziell auf Ihre Anforderungen zugeschnitten sind. Darüber hinaus ermöglichen wir eine schnelle und zuverlässige Integration unserer IPs in das gewünschte Gesamtsystem in Technologien von 350 nm bis 22 nm. Unsere Kunden profitieren von einer Vielzahl an IPs aus unserer langjährigen Projekterfahrung. Das Fraunhofer IIS Portfolio reicht von Mixed-Signal-IPs wie ADUs bis hin zu komplexeren Schaltungsblöcken wie einem Ultra-Low-Power-Empfänger mit kurzer Latenz.

Wir entwickeln gerne neue Makros oder passen vorhandene IPs an Ihre Anforderungen an.

Unser Service Portfolio:

Kundenspezifische funktionale Anpassungen
Schnelle Integration
Entwicklung von IPs in Zieltechnologie
Portierung
Kundensupport

Fraunhofer IIS: IP und IP Cores

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ADC

IP Name	Description and Key Parameters	Process	Availability
ADC11b100kS22nm	11 Bit 100 kS/s Ultra-Low Power SAR ADC	GlobalFoundries 22FDX	silicon proven
ADC14b100kS180nm	14 Bit 100 kS/s Sigma-Delta ADC	XFAB XT018	silicon evaluated
ADC12b002MS180nm	12 Bit 2 MS/s Sigma-Delta ADC	XFAB XT018	silicon evaluated
ADC07b006GS055nm	7 Bit 6 GS/s Folding ADC	Fujitsu 55 nm CS250L	silicon evaluated
ADC10b040MS180nm	10 Bit 40 MS/s Pipeline ADC	AMS C18	silicon proven
ADC16b013kS180nm	16 Bit 13 kS/s Cyclic ADC	XFAB XH018	silicon evaluated
ADC12b017kS180nm	12 Bit 17 kS/s Cyclic ADC	XFAB XH018	silicon evaluated
ADC12b054kS180nm	12 Bit 54 kS/s Cyclic ADC	XFAB XH018	silicon evaluated
ADC12b040MS180nm	12 Bit 40 MS/s Pipeline ADC	XFAB XH018	silicon proven
ADC15b008kS180nm	15 Bit 8 kS/s Sigma-Delta ADC	XFAB XH018	silicon proven
ADC15b192kS180nm	15 Bit 192 kS/s Sigma-Delta ADC	XFAB XH018	silicon proven
ADC13b010kS180nm	Ultra-Low-Power 6 - 13 Bit 1-10 kS/s 1.9 µW SAR ADC	XFAB XT018	silicon evaluated
ADC16b010kS350nm	16 Bit 10 kS/s Incremental Delta-Sigma ADC	AMS H35	silicon evaluated
ADC12b020MS350nm	12 Bit 20 MS/s Pipeline ADC	XFAB XH035	silicon proven

DAC

IP Name	Description and Key Parameters	Process	Availability
SDDAC16b008kS22nm	16-bit 8 kS/s Sigma-Delta DAC	Globalfoundries 22nm FDX, GF40nm, GF28SLP, XFAB180nm
DAC08b006GS055nm	8 Bit 6 GS/s Current Steering DAC	Fujitsu 55 nm CS250L	silicon evaluated
DAC12b001MS180nm	12 Bit 1 MS/s DAC with voltage output	AMS C18	silicon proven

RF

IP Name	Description and Key Parameters	Process	Availability
VCO5G0_55nm	5 GHz VCO	GLOBALFOUNDRIES 55LPE	silicon evaluated
MIX1G5_55nm	1.5 GHz RF-buffered Mixer	GLOBALFOUNDRIES 55LPE	silicon evaluated
RF_WakeUp_Rx	Ultra-low power RF receiver/ WakeUp receiver	GLOBALFOUNDRIES 130LP	silicon evaluated
LNA433_130nm	433 MHz LNA	GLOBALFOUNDRIES 130LP	silicon evaluated
LNA868_130nm	868 MHz LNA	GLOBALFOUNDRIES 130LP	silicon evaluated
LNA2G4_130nm	2.4 GHz LNA	GLOBALFOUNDRIES 130LP	silicon evaluated
VCO2G5_130nm	2.5 GHz VCO	GLOBALFOUNDRIES 130LP	silicon evaluated
MIXSub1G_130nm	Sub-1 GHz Mixer	GLOBALFOUNDRIES 130LP	silicon evaluated
MIX2G4_130nm	2.4 GHz Mixer	GLOBALFOUNDRIES 130LP	silicon evaluated
LDO3V3_1V5_130nm	Low Power 3.3 V to 1.5 V LDO	GLOBALFOUNDRIES 130LP	silicon evaluated
PLL160M40M180nm	160 MHz output frequency PLL	AMS C18	silicon evaluated

supply

IP Name	Description and Key Parameters	Process	Availability
LDO3V3_1V5_130nm	Low Power 3.3 V to 1.5 V LDO	GLOBALFOUNDRIES 130LP	silicon evaluated

AFE

IP Name	Description and Key Parameters	Process	Availability
AFE13b010kS180nm	Ultra-Low-Power 6-13 Bit 0.5-10 KS/s 10μW Analog-Frontend	XFAB XT018	silicon evaluated

Crypto

IP Name	Building Block	Description	IP Format	Technology	Interface compatibility	Availability
FHIISSCASC22	Symmetric Crypto ASCON	Light-weight NIST standardized Crypt-Algorithms für IoT devices	SystemVerilog	22	TL-UL	Verification complete
FHIISASCPQ22	Asymmetric Crypto PQ:SPHINX+, PQ:Dilithium	NIST selected PQ digital signature schemes	SystemVerilog	22	TL-UL	Verification complete

Security

IP Name	Building Block	Description	IP Format	Technology	Interface compatibility	Availability
FHIISSAESAC22	AES (symmetric encription algorithm accelerator)	Fast and energy efficient encryption algorithm, NIST standardized	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISBNAC22	Big-Number Accelerator (coprocessor for asymmetric cryptographic operations like RSA or Elliptic Curve Cryptography (ECC).)	Features a 256-bit wide data path for accelerating wide integer arithmetic in IoT and secure silicon Root of Trust (RoT) applications, offering significant performance gains over software implementations	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISHMAC22	HMAC (SHA2 hashing algorithm accelerator)	Hash-based Message Authentication Code, well-established standard widely used in web security and digital signatures	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISKMAC22	KMAC (SHA3 hashing algorithm accelerator)	Advanced features and flexibility, making it suitable for modern applications like blockchain and secure messaging	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISTRNBG	Entropy Source (True Random Bit Generator - TRBG)	A TRNG is a function or device based on an unpredictable physical phenomenon, called an entropy source, that is designed to generate non-deterministic data to seed security algorithms.	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISCSRNG22	CSRNG - Cryptographically Secure Random Number Generator (RNG)	The CSRNG IP supports BSI AI31 and NIST SP800-90A standards for both deterministic (DRNG) and true random number generation (TRNG).	SystemVerilog	22	TL-UL	Test chip validation complete

Security Macros

IP Name	Building Block	Description	IP Format	Technology	Interface compatibility	Availability
FHIISTNRGNSECS22	TRNG Noise Source + Entropy + CS RNG	This macro comprises a full PTRNG (Physical True Random Number Generator)	SystemVerilog	22	TL-UL	Verification complete
FHIISLCMOTPCN22	Life Cycle Management, OTP + Life Cycle (controller)	Full support for Life-Cycle states and funcational isolation based on currrent state (e.g. at foundry, in the field, in operation etc.)	SystemVerilog	22	TL-UL	Verification complete

Memory

IP Name	Building Block	Description	IP Format	Technology	Interface compatibility	Availability
FHIISSMRM22	Secure NVM (MRAM)	MRAM based non volatile storage with isolated and secure information partitions	SystemVerilog	22	TL-UL	Design complete
FHIISMSMWC22	Flash MRAM Wrapper + controller	Support and wrapping logic for MRAM_eFLASH_256Kx78B, STT MRAM Technology, 256K x 78 Bits and similar interface MRAMs.	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISEFWC22	eFUSE Wrapper + controller	Support and wrapping logic for 22FDSOI 128X32 EFUSE Macro FB_22FDX_128X32 and similar interface eFuses.	SystemVerilog	22	TL-UL	Test chip validation complete

Communication

IP Name	Building Block	Description	IP Format	Technology	Interface compatibility	Availability
FHIISGPIO22	GPIO	verified Standard Bus	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISI2C22	I2C	verified Standard Bus	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISSPI22	SPI-Device ans Host	verified Standard Bus	SystemVerilog	22	TL-UL	Test chip validation complete
FHIISUART22	UART	verified Standard Bus	SystemVerilog	22		Test chip validation complete

CPUs

IP Name	Building Block	Description	IP Format	Technology	Interface compatibility	Availability
FHIISR5IBX22	IBEX with Lockstep	supports a robust dual-lockstep configuration designed for high-reliability and security applications. Consists of two identical cores running in parallel and comparing their outputs to detect faults and mitigate potential security attacks.	SystemVerilog	22	TL-UL	Verification complete

Processing

IP Name	Building Block	Description	IP Format	Technology	Interface compatibility	Availability
FHIISAUICC22	Aurora Inter-chip Communication	Inter- chip/FPGA highspeed data interface with 32Gpbs gross bandwidth. Soft-core, ASIC proven with PHY from WCC on 22FDX. 4 physical lanes @8GHz. 128b parallel interface to SoC	SystemVerilog	22	Non Standard Interface	Verification complete
FHIISDFE22	DFE	7-tap decision feedback equalizer (frequency optimized speculative implementation: 2GHz @ 22FDX) for PAM-4. Sample resolution: fixed-point 5.8, coefficient resolution: fixed-point 2.8.	SystemVerilog	22	Non Standard Interface	Verification complete
FHIISFFE22	FFE	8 times parallel 8-tap feed forward equalizer. Input resolution: fixed-point 5.3. Output resolution: fixed-point 5.8. Coeff-resolution: fixed-point ?.?	SystemVerilog	22	Non Standard Interface	Verification complete
FHIISPRNG22	PRBS generators	Easy adaptable PRBS-generators for PRBS-7, PRBS-9, PRBS-15, PRBS-23, PRBS-31	SystemVerilog	22	Non Standard Interface	Verification complete
FHIISPBSC22	4-fold parallel bit sequence correlator	verified correlator for bit sequences	SystemVerilog	22	Non Standard Interface	Verification complete