IP Cores and Macros

In the development of ASIC and SoC solutions, IPs and macros reduce the development time, design risk and costs. As an independent design house, we can offer our customers solutions tailored to their requirements. In addition, we enable fast and reliable integration of our IPs into the desired overall system in various semiconductor technologies from 350 nm down to 22 nm. Our customers benefit from a wide variety of IPs which were created as part of our project expertise over many years. The Fraunhofer IIS portfolio ranges from mixed-signal IPs such as ADCs all the way to more complex circuit blocks, such as an ultra-low-power receiver with short latency.  

We would be delighted to develop new macros for you or adapt existing IPs to your requirements.

 

Our service portfolio:

  • Customized adaptation to improve the performance of your system
  • Quick integration into overall system
  • Development of IPs in desired technology
  • High reliability thanks to silicon proven IPs
  • Customer support

Fraunhofer IIS: IP Cores

IP Name

Description and Key Parameters Process Availability
ADC07b006GS055nm 7 Bit 6 GS/s Folding ADC Fujitsu 55 nm CS250L silicon evaluated
ADC10b040MS180nm 10 Bit 40 MS/s Pipeline ADC AMS C18 silicon proven
ADC16b013kS180nm

16 Bit 13 kS/s Cyclic ADC

XFAB XH018
silicon evaluated
ADC12b017kS180nm 12 Bit 17 kS/s Cyclic ADC XFAB XH018 silicon evaluated
ADC12b054kS180nm 12 Bit 54 kS/s Cyclic ADC XFAB XH018 silicon evaluated  
ADC12b040MS180nm 12 Bit 40 MS/s Pipeline ADC XFAB XH018 silicon proven  
ADC15b008kS180nm 15 Bit 8 kS/s Sigma-Delta ADC XFAB XH018 silicon proven
ADC15b192kS180nm 15 Bit 192 kS/s Sigma-Delta ADC XFAB XH018 silicon proven
ADC13b010kS180nm Ultra-Low-Power 6 - 13 Bit 1-10 kS/s 1.9 µW SAR ADC XFAB XT018 silicon evaluated
ADC16b010kS350nm 16 Bit 10 kS/s Incremental
Delta-Sigma ADC
AMS H35 silicon evaluated
ADC12b020MS350nm 12 Bit 20 MS/s Pipeline ADC XFAB XH035 silicon proven

IP Name Description and Key Parameters Process Availability
DAC08b006GS055nm 8 Bit 6 GS/s Current Steering DAC Fujitsu 55 nm CS250L silicon evaluated
DAC12b001MS180nm 12 Bit 1 MS/s DAC with voltage output AMS C18 silicon proven

IP Name Description and Key Parameters Process Availability
VCO5G0_55nm 5 GHz VCO GLOBALFOUNDRIES 55LPE silicon evaluated
MIX1G5_55nm 1.5 GHz RF-buffered Mixer GLOBALFOUNDRIES 55LPE silicon evaluated
RF_WakeUp_Rx Ultra-low power RF receiver/ WakeUp receiver GLOBALFOUNDRIES 130LP silicon evaluated
LNA433_130nm 433 MHz LNA GLOBALFOUNDRIES 130LP silicon evaluated  
LNA868_130nm 868 MHz LNA GLOBALFOUNDRIES 130LP silicon evaluated  
LNA2G4_130nm 2.4 GHz LNA GLOBALFOUNDRIES 130LP silicon evaluated 
VCO2G5_130nm 2.5 GHz VCO GLOBALFOUNDRIES 130LP silicon evaluated
MIXSub1G_130nm Sub-1 GHz Mixer GLOBALFOUNDRIES 130LP silicon evaluated
MIX2G4_130nm 2.4 GHz Mixer GLOBALFOUNDRIES 130LP silicon evaluated
LDO3V3_1V5_130nm Low Power 3.3 V to 1.5 V LDO GLOBALFOUNDRIES 130LP silicon evaluated
PLL160M40M180nm 160 MHz output frequency PLL AMS C18 silicon evaluated 

IP Name Description and Key Parameters Process Availability
LDO3V3_1V5_130nm Low Power 3.3 V to 1.5 V LDO GLOBALFOUNDRIES 130LP silicon evaluated

Contact

Loreto Mateu

Contact Press / Media

Dr. Loreto Mateu

Group Manager

Fraunhofer IIS
Am Wolfsmantel 33
91058 Erlangen, Germany

Phone +49 9131 776-4456

Fax +49 9131 776-4499

Torsten Reich

Contact Press / Media

Dr. Torsten Reich

Group Manager Integrated Sensor Electronics

Fraunhofer IIS, Division Engineering of Adaptive Systems
Zeunerstraße 38
01069 Dresden, Germany

Phone +49 351 4640-761

Michael Geyer

Contact Press / Media

Michael Geyer

Marketing and Sales

Fraunhofer IIS
Am Wolfsmantel 33
91058 Erlangen, Germany

Phone +49 9131 776-4406

Fax +49 9131 776-4499