How chip designers at Fraunhofer IIS help shaping the future of microelectronics in Europe.

March 22, 2024

The prevailing shortage of semiconductors and chips is exerting a profound influence on our industry. The heavy reliance on suppliers and value chains in Asia and America poses a substantial challenge to the economies of Bavaria, Germany, and Europe as a whole. In light of this situation, we are committed to making a meaningful contribution towards reestablishing chip design in Europe. The chip designers at Fraunhofer IIS play a crucial role in this endeavor by making significant contributions.

Focus on Sustainability: Dr. Markus Eppel

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Dr. Markus Eppel is head of the Advanced Analog Circuits group at Fraunhofer IIS. His primary focus revolves around the development of energy-efficient chips using analog-digital design and neuromorphic hardware.

Dr. Eppel started his academic journey by specializing in microelectronics during his electrical engineering studies at TU Darmstadt. Throughout his educational tenure, he served as a student assistant at Dialog Semiconductor and Austria Microsystems, located near Graz in Austria. Following the completion of his diploma in electrical engineering and information technology at TU Darmstadt, with a particular emphasis on microelectronics, he went on to attain his doctorate from Friedrich-Alexander-Universität Erlangen-Nürnberg. During his doctoral research, Dr. Eppel focused on the subject of "Power-saving integrated UHF super regenerative receiver with high tolerance to dynamic interference signals."

On the way to a doctorate - Christian Kohlbrenner

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Christian Kohlbrenner works in the Magnetic Sensor Systems group.

His current focus is on the pre-development of new circuits for magnetic field sensors and test preparation. In addition to his professional commitments, he is currently pursuing his doctoral thesis. He studied electrical engineering and information technology at Aschaffenburg University of Applied Sciences, now Aschaffenburg University of Technology, and completed his mandatory internship in the field of hardware development. During his Master's degree, he was a student assistant and Master's student at Fraunhofer IIS, gaining valuable experience in the field of chip design.

Top research thanks to top equipment – Meet Jens Länglacher

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Jens Länglacher is a member of the Wireline Communication Circuits group. His current focus is on the evaluation and verification of high-speed chips designed in-house and the design of control hardware for a quantum computer.

He pursued his studies in physics at the University of Augsburg and served as a student assistant at the University of Augsburg during his master's thesis. During this time, his responsibilities included overseeing a superconductor internship and the investigation of superconductors.

A look behind the scenes - Preethi Vigneesha Govindaraj

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Preethi Vigneesha Govindaraj is a vital member of the Integrated Sensor Electronics group, specializing in high-speed analog design

She studied Electrical and Electronics Engineering in Chennai, Tamilnadu, India and completed her Master's degree in Nanoelectronic Systems at TU Dresden. During her academic pursuit, she wrote her master's thesis at the Fraunhofer Institute for Electronic Microsystems and Solid State Technologies EMFT in Munich and started as a student assistant at Fraunhofer IIS.

Exploring the joy of tinkering - Anne Engerer

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Anne Engerer, a member of the Integrated Sensor Signal Processing group, began her studies in medical engineering at the Friedrich-Alexander University of Erlangen-Nuremberg and transitioned her focus to electrical engineering, electronics and information technology (EEI) after the second semester, specializing in microelectronics.

She first came into contact with chip design during her internship at the Chair of Technical Electronics. Over five years, Anne was a student assistant at Fraunhofer IIS and wrote her master's thesis at eesy-ic on the circuit design and layout of two two-stage operational amplifiers in CMOS technology (chip design).

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