Verilog-AMS Training Course


The course provides an introduction to behavioral modeling with Verilog-AMS. Participants are introduced to the principles of the language and shown basic language constructs for describing analog and mixed analog-digital system components.

The program focuses on the development and use of behavioral models to test specifications as part of top-down design. Exercises related to this content can be factored in on request.

The starting point for the exercises is Verilog-AMS model description. Schematic entry tools are not used. Digital Verilog knowledge is only conveyed to the extent that it is required for the exercises.

Course Objectives

Participants will obtain an overview of the possibilities offered by behavioral modeling using Verilog-AMS. They will be able to understand and apply current Verilog-AMS models. In addition, they will carry out modifications of existing Verilog-AMS models and be able to create simple models for their own tasks.

Key Aspects

  • Teaching basic language constructs for describing analog and mixed analog-digital  systems using Verilog-AMS
  • Modeling approaches for electric/non-electric systems
  • Analysis of existing Verilog-AMS descriptions
  • ·Expansion of existing Verilog-AMS models
  • Guidance on how to create more complex models
  • Sharing experience and insights concerning the use of Verilog-AMS as part of system simulation

Course Participants

The course is aimed at those who want to use Verilog-AMS for system specification. Ideally, participants will have some previous knowledge of analog circuit simulation using SPICE or similar programs, but this is not essential.


Two days with eight hours of teaching each day, on request at your company’s location or held at our facility in Dresden.

Course Language