The course provides an introduction to behavioral modeling with Verilog-AMS. Participants are introduced to the principles of the language and shown basic language constructs for describing analog and mixed analog-digital system components.
The program focuses on the development and use of behavioral models to test specifications as part of top-down design. Exercises related to this content can be factored in on request.
The starting point for the exercises is Verilog-AMS model description. Schematic entry tools are not used. Digital Verilog knowledge is only conveyed to the extent that it is required for the exercises.