Secure System on Chip

In the Secure System on Chip focus area, the BCDC is researching an open and secure processor platform that is characterized by hardware/software co-design. In addition, the platform combines the Secure RISC-V processor with a secure element to maximize security through tamper-proof hardware.

Building on a comprehensive ecosystem as a basise​

• RISC-V processor subsystem 64-bit CVA6 (single-, multi-core, superscalar), 32-bit Ibex ULP
• RISC-V Secure Element (Basis: OpenTitan)
• Secure OS, secure boot, FW updates, hypervisor
• Memory subsystem incl. multicore cache coherence
• Peripherals
• Crypto accelerator, incl. PQC
• Further IP incl. sensors

Design support for regulated markets

• Common Criteria​
• NIS2​
• Safety​
• ISO 62443​
• CRA​
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• Low-threshold technical consulting from initial interviews to feasibility and implementation studies to complete system architecture and specification
• Scalable and secure system designs
• Optimized, application-specific accelerators with minimal power requirements
• Provision and integration of pre-developed, configurable and verified IP blocks
• Large portfolio of available semiconductor technologies (55nm to 4nm)
• Adapted SW and OS components for RISC-V, for efficient access to software ecosystems
• Investigation into the hardware security of RISC-V and other SoCs
• Investigation of security-relevant source code for RISC-V