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On the Way to Artificial Intelligence

Neuromorphic Hardware

What is neuromorphic hardware?

Neuromorphic hardware uses specialized computing architectures that reflect the structure (morphology) of neural networks from the bottom up: dedicated processing units emulate the behavior of neurons directly in hardware, and a web of physical interconnections (bus-systems) facilitate the rapid exchange of information. This concept is inspired by the human brain, where biological neurons and synapses work together in a similar way. Specialized neuromorphic devices are less flexible than universal central processing units (CPUs), but offer exceptional performance and energy efficiency during the training and inference for deep neural networks.


Why neuromorphic hardware?

Conventional computers implement the so-called von Neumann architecture, which comprises processing cores that sequentially execute instructions, and process data stored in some centralized memory. This means that the computing performance of such systems is limited by the data rate, which can be transferred between the processing unit and an external memory unit (von Neumann bottleneck). With more and more demanding applications, the interest in high-performance computing has shifted towards increased parallelism in the form of multi-core architectures. However, the ability to parallelize computations is fundamentally bounded by the access to shared memory resources. Recent advances in deep learning test these limits, because the highly parallel structure of deep neural networks requires specific distributed memory access patterns that are difficult to map efficiently onto conventional computing technology. Neuromorphic hardware addresses this challenge and helps to give artificial intelligence (AI) to devices and systems.

Neuromorphic architectures

Just like the field of neural networks, the corresponding neuromorphic hardware designs are very diverse and range from networks with binarized weights in digital hardware to analog in-memory accelerators of convolutional neural networks and event-based spiking neural network accelerators. The optimal design choice is determined by the application at hand and its specific requirements: energy efficiency, latency, flexibility or peak performance.

Analog neuromorphic hardware design

Since the earliest attempts of neuromorphic hardware design in the 1950s, analog circuits have been used to implement neural networks in hardware. In this approach, the real-valued quantities of the neural network model are represented by real-valued physical quantities like analog voltages, currents or charges, and operations like multiplication and addition are realized directly by application of physical laws, i.e. Ohm’s and Kirchhoff’s laws.

The numerous coefficients of the neural networks are either hardwired by appropriately chosen resistive elements or can be programmed into novel memory cells distributed throughout the circuit, which drastically relaxes the bottleneck of memory-transfer.

Applications for analog accelerators

Analog circuits are rigid and highly optimized for one specific network architecture, but extremely power-efficient and fast due to the asynchronous in-memory computing. Therefore, analog neuromorphic hardware is a promising solution for highly optimized next-generation computing and signal processing – in particular for ultra-low-power and real-time applications. A typical use case for analog accelerators is the processing of low-dimensional senor signals, e.g. in audio, medical and condition monitoring applications.

Digital neuromorphic hardware design

In digital deep learning accelerators, dedicated logic circuits, rather than centralized and generic arithmetic logic units, carry out exactly those operations required to simulate a deep neural network. This allows for an optimized design that can leverage the highly parallel structure of neural networks to speed up inference and learning.

By utilizing novel memory cells distributed throughout the circuit, the memory bandwidth can be greatly reduced, which allows for the processing of large amounts of data at high speeds.

Applications for digital accelerators

Implementations range from dedicated ASICs with very low power consumption via generic accelerators for a variety of network architectures to extremely flexible, FPGA-based solutions. Due to their flexibility, extensibility, scalability and easy integration into digital platforms, digital deep learning accelerators are ideally suited for rapidly developing use cases, reconfigurable and cloud-connected devices, or high-performance computing applications. Digital accelerators are mainly used for the processing of big or high-dimensional data, e.g. in high-performance computing for image, video or medical data processing and analysis.

Spiking neuromorphic hardware design

The design of custom neuromorphic hardware enables novel neural network architectures such as spiking neural networks (SNN), which rely on a mathematical framework that defies the conventional computing paradigm.

In these networks, the exchange of information relies on binary pulse- or spike-based communication, where each neuron communicates only relevant events by brief stereotypical pulses.

Applications for spiking neural networks

This mode of event-based operation is difficult to realize in conventional von-Neumann computer architectures, but can be very efficiently implemented in an analog or mixed-signal hardware stack. The development of spike-based neuromorphic hardware promises great performance gains in terms of energy consumption and latency and therefore opens an entirely new avenue for ultra-low power applications. Spiking neural network accelerators can be profitably applied for low-power processing of time series, e.g. in speech or video analysis and predictive maintenance.

Bringing AI to hardware – consulting, design and implementation

Fraunhofer IIS has long-standing experience in the application of machine learning to various use cases. Our experts employ neuromorphic hardware to speed up the computation in embedded devices.

Our offer includes consulting for your machine learning use case and suitable neuromorphic hardware as well as the design and implementation of modules for your devices that employ neuromorphic hardware.

We find the optimum neuromorphic design for your specific use case.

Overview of neuromorphic hardware

The table provides an overview of hardware platforms and their strengths and drawbacks with respect to neuromorphic computing:

  • General Purpose Central Processing Units (GP CPUs)
  • GP CPUs with accelerators
  • General Purpose Graphics Processing Units (GP GPUs)
  • Dedicated hardware (ASICs: Application Specific Integrated Circuits)
  • Field-Programmable Gate Arrays (FPGAs)
  • Digital Signal Processors (DSPs)
Table with overview of neuromorphic hardware
© Fraunhofer IIS

Professional publications and talks

Neuromorphic Hardware

Hardware for neural networks: overview of different approaches and current developments


AI chips and IP cores

Overview of deep learning inference accelerators

Source: Elektronik, 9/2019

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Making spiking neurons more succinct

Talk from Johannes Leugering during the Neuro-Inspired Computational Elements Conference (NICE 2021)

"Making spiking neurons more succinct with multi-compartment models" was awarded with a best talk award.

Current research projects

Further information



Neuromorphic hardware


Embedded Machine Learning

Implementation and integration of machine learning algorithms on embedded devices


Reference project

Reconfigurable hardware platform for AI-based sensor data processing for autonomous driving


Machine Learning at Fraunhofer IIS

Overview of the topic "Machine Learning" at Fraunhofer IIS