Standards-based chiplets on Samsung’s 5 nm process technology

Design work supports introduction of chiplet technology, including for smaller batches of electronic products 

Producing a chiplet interface from chip to chip nowadays is economical, especially for mass-produced applications. However, this largely excludes customer-specific implementation for product groups with smaller and medium batch sizes; for these, the use of chiplets is currently still too costly and unprofitable. The advantages of the technology, such as the greater degrees of freedom in selecting suitable manufacturing technologies for circuits, remain broadly untapped in this market segment.

To change this, we at the Engineering of Adaptive Systems EAS division are working on developing customizable chiplet-based solutions. However, making them safe and efficient calls for uniform standards, such as with regard to the die-to-die interface. This is the only way to successfully integrate circuits from different manufacturers, including for small production runs, and to avoid problems during chip assembly. 

“We are delighted to work with Fraunhofer IIS/EAS on implementing their interface IP in our 5 nm process technology,” says Kevin Yee, Senior Director of Marketing, Foundry IP and Ecosystem from Samsung Electronics. “As a leading IP partner in our SAFETM ecosystem, and a provider of BoW-based interface IPs, which is also of interest to Samsung Foundry, we plan to work together and find ways of supporting our mutual customers and the industry.”

To this end, the Fraunhofer design team used the Open Compute Project’s BoW (Bunch of Wires) standard. “As part of this work, we even managed to implement a data rate of 16 Gbit/s per lane – the highest rate specified by the BoW standard. We believe this provides an excellent basis for implementing forward-looking solutions for our customers,” adds Andy Heinig, chiplet expert at EAS.